VHDL覚書

・・・やった。
VHDLでやっと逓倍パルス信号が出せた・・・!!

参考までにソースをうpしてみます。
汚いソースコードなので、全く参考にならないかもしれません。
というか、需要が在るのかどうかも不明です...

entity TWICE_PULSE is
port(
CLK: in std_logic;
RESET: in std_logic;
KIDO_R, KIDO_B, KIDO_G: in std_logic_vector(3 downto 0);
OUT_R, OUT_B, OUT_G: out std_logic

    • R_Y, B_Y, G_Y: out std_logic

);
end TWICE_PULSE;

architecture Behavioral of TWICE_PULSE is
signal TempQ_R: std_logic_vector(3 downto 0);
signal TempQ_B: std_logic_vector(3 downto 0);
signal TempQ_G: std_logic_vector(3 downto 0);
signal E_R: std_logic_vector(3 downto 0);
signal E_B: std_logic_vector(3 downto 0);
signal E_G: std_logic_vector(3 downto 0);
begin
process( CLK, RESET )
begin
if( RESET = '1' ) then
TempQ_R <= ( others => '0' );
elsif( CLK'event and CLK = '1' ) then
TempQ_R <= TempQ_R + '1';
end if;
end process;
process( CLK, RESET )
begin
if( RESET = '1' ) then
TempQ_B <= ( others => '0' );
elsif( CLK'event and CLK = '1' ) then
TempQ_B <= TempQ_B + '1';
end if;
end process;
process( CLK, RESET )
begin
if( RESET = '1' ) then
TempQ_G <= ( others => '0' );
elsif( CLK'event and CLK = '1' ) then
TempQ_G <= TempQ_G + '1';
end if;
end process;

E_R(0) <= TempQ_R(0) and (not TempQ_R(1)) and (not TempQ_R(2)) and (not TempQ_R(3));
E_R(1) <= TempQ_R(1) and (not TempQ_R(2)) and (not TempQ_R(3));
E_R(2) <= TempQ_R(2) and (not TempQ_R(3));
E_R(3) <= TempQ_R(3);

E_B(0) <= TempQ_B(0) and (not TempQ_B(1)) and (not TempQ_B(2)) and (not TempQ_B(3));
E_B(0) <= TempQ_B(0) and (not TempQ_B(1)) and (not TempQ_B(2)) and (not TempQ_B(3));
E_B(1) <= TempQ_B(1) and (not TempQ_B(2)) and (not TempQ_B(3));
E_B(2) <= TempQ_B(2) and (not TempQ_B(3));
E_B(3) <= TempQ_B(3);

E_G(0) <= TempQ_G(0) and (not TempQ_G(1)) and (not TempQ_G(2)) and (not TempQ_G(3));
E_G(1) <= TempQ_G(1) and (not TempQ_G(2)) and (not TempQ_G(3));
E_G(2) <= TempQ_G(2) and (not TempQ_G(3));
E_G(3) <= TempQ_G(3);

OUT_R <= (E_R(3) and KIDO_R(3))or(E_R(2) and KIDO_R(2))or(E_R(1) and KIDO_R(1))or(E_R(0) and KIDO_R(0));
OUT_B <= (E_B(3) and KIDO_B(3))or(E_B(2) and KIDO_B(2))or(E_B(1) and KIDO_B(1))or(E_B(0) and KIDO_B(0));
OUT_G <= (E_G(3) and KIDO_G(3))or(E_G(2) and KIDO_G(2))or(E_G(1) and KIDO_G(1))or(E_G(0) and KIDO_G(0));

end Behavioral;

【解説編】
入力された4ビットの信号を逓倍パルスで出力する回路です。
4ビットアップカウンタの信号を利用して4ビットの入力された信号とorして逓倍パルスを得ています。